The present invention relates to non-volatile flash memory (“NVM”) semiconductor devices, which can continually store information even in the absence of electricity supply. More particularly, the invention relates to NVM semiconductor devices having two-bits per cell employed in a not-and-gate (NAND) array.
Multi-level, or multi-bit, flash memory cells provide a solution for increasing the amount of data that can be stored on a memory device without consuming more space. Whereas a single-bit cell can store only two states, “on” and “off” (typically labeled “0” and “1”), a cell having n bits and using binary encoding is capable of storing up 2n states. Thus, a two-bit cell may store data in four discrete states, “00”, “01”, “10” and “11” which is distinctly more efficient that the “0” or “1” state alone.
Conventional two-bits per cell NVM semiconductor devices have a narrow “window of operation” after programming. This operational window is generally described as the difference in the threshold voltage (Vt) of a programmed cell bit as compared to the Vt of the un-programmed (erased) state. In a two-bit memory cell the operational window is also known as the second bit window of operation. The second bit window of operation is generally described as the second-bit effect on the Vt of one bit not undergoing a programming action by the programming of the other bit associated with the same cell (the target bit). For example, as a left bit is programmed from its initial state with Vti to its programmed state with a programmed Vt, the Vt of the right bit, which is not being programmed, undergoes an undesired “shift.” Meaning the right bit Vt (voltage) is adjusted higher for the same bit state that existed before the left bit was programmed. The result is a narrow operational window for that bit.